1. Technical Field
The present invention relates to binary memories, and in particular relates to a method and a circuit arrangement for reading out binary memory cell signals from a memory cell array and for storing binary memory cell signals in a memory cell array.
2. Background Art
In digital memories (RAM, DRAM, SRAM), an information item stored digitally in the form of binary memory cell signals has to be transferred to an output terminal of the circuit arrangement (chip). Memory cells are conventionally arranged in memory cell arrays having a size of 512xc3x97128, for example. In this case: 512 word lines can be activated in order to load a binary information item into the respective memory cell array. In the circuit arrangement specified above, 128 bit line pairs serve for reading out the corresponding binary information or for transferring binary memory cell signals from the memory cell array and for storing binary memory cell signals in the memory cell array.
A bit line pair usually comprises two lines which have complementary binary signal states. On account of the usually highly complex circuit arrangement, the bit line pairs cannot be used for forwarding binary memory cell signals directly to externally accessible Output terminals. Besides a complex line structure, the binary memory cell signals additionally have to be regenerated or amplified in sense amplifiers or latches. In this case, it is necessary to arrange the sense amplifiers together with various switching transistor pairs in order that an information item present on bit line pairs is finally conducted away to an output terminal.
FIG. 1 shows a known circuit arrangement in which eight sense amplifiers S/A interact with a main data line switching transistor pair MDQS. The memory cell signals transferred from corresponding memory cell S arrays are present on respective bit line pairs designated by  less than 0 greater than  to  less than 7 greater than , where BL designates a bit line pair, t designates a top memory cell array, b following the symbol BL designates a bottom memory cell array, and a preceding b designates a complementary line of the bit line pair (bar).
Memory cell signals which are present on the top bit lines t and originate from a cop memory cell array or binary memory cell signals which are present on the bottom bit line pairs b and originate from a bottom memory cell array can optionally be applied to the sense amplifiers S/A. In this case, a main data line switching transistor pair MDQS serves for switching binary memory cell signals which are present on local data line pairs to a main data line pair, at least one sense amplifier S/A being activated.
On account of possible interference and influencing of adjacent data lines, the lines of the bit line pairs must have a specified minimum distance which depends on the desired specifications for the memory cell array and technological fabrication processes.
FIG. 1 shows by way of example a fixed data line distance, it being discernible that bit line pairs arranged in the vicinity of the main data line switching transistor pair MDQS, here the bit line pairs designated with the index numbers 3 and 4, have bevels, which are disadvantageous for customary fabrication processes.
A further disadvantage of such bevels is that in principle usable area of the circuit arrangement, i.e. chip area, is wasted.
Yet another disadvantage of the bevels in bit data line pairs is that undesirable edge effects occur.
Furthermore, it is inexpedient that a regular wiring of the bit line pairs with the sense amplifiers is disturbed by a centrally arranged main data line switching transistor pair MDQS.
Furthermore, an arrangement of main data line switching transistor pairs according to FIG. 1 disadvantageously enlarges a mutual distance between the memory cell arrays, whereby a chip size is increased overall.
Consequently, it is an object of the present invention to provide a circuit arrangement in which main data line switching transistor pairs are arranged in such a way that bit line pairs can be designed regularly, and that, in particular, bevels in bit line pairs are avoided, whereby utilization of a chip area is improved.
This object is achieved according to the invention by means of a method according to claim 1 and also a circuit arrangement having the features of claim 4.
The heart of the invention consists in al least one main data line switching transistor pair being placed in through-plating regions which are arranged between individual memory cell arrays.
The invention""s method for reading out binary memory cell signals from a memory cell array and for storing binary memory cell signals in a memory cell array has the following steps:
a) application of at least one binary memory cell signal from at least one memory cell arranged in a memory cell array to a bit line pair;
b) switching-through of a binary memory cell signal from the memory cell of a memory cell array via a bit line pair to at least one sense amplifier, at least one memory cell array switching transistor pair being used, in a manner dependent on at least one memory cell array control signal fed via at least one memory cell array control line;
c) switching-through of a binary output signal of the sense amplifier to a local data line pair as a binary intermediate signal by means of at least one local data line switching transistor pair in a manner dependent on a column control signal fed via a column control line;
d) switching-through of the binary intermediate signal of the local data line pair to at least one main data line pair by means of at least one main data line switching transistor pair in a manner dependent on a row control signal fed via a row control line; and
e) outputing of a binary output signal via the main data line pair to an output terminal.
Advantageous developments and improvements of the respective subject matter of the invention can be found in the subclaims.
In accordance with one preferred development of the present invention, at least one main data line switching transistor pair, which provides a switching-through of binary memory cell signals from local data line pairs to main data line pairs, is provided in through-plating regions arranged between memory cell arrays, thereby producing a regular arrangement of bit line pairs across the memory cell array.
In accordance with a further preferred development of the present invention, the bit line pairs are provided rectilinearly with only minimal bevels, so that a chip area can be reduced.
The invention""s circuit arrangement for reading out binary memory cell signals from a memory cell array arranged in a memory cell area and for storing binary memory cell signals in the memory cell array furthermore has:
a) at least one bit line pair for connecting at least one memory cell of a memory cell array to at least one memory cell array switching transistor pair;
b) at least one sense amplifier connected to the memory cell array switching transistor pair, said sense amplifier being arranged symmetrically with respect to the bit line pairs of memory cell areas whose memory cell arrays are connected to the sense amplifier;
c) at least one local data line switching transistor pair for switching the binary output signal of the sense amplifier to at least one local data line pair; and
d) at least one main data line switching transistor pair for connecting the local data line pair to at least one main data line pair, at least one main data line switching transistor pair being arranged in through-plating regions between memory cell arrays.